We are looking for dynamic leaders who can develop and drive technical solutions with our customers so that we grow our market share and contribute to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. As Senior Analog RF IC Architect, the individual will be involved in developing key high speed mixed signal designs from architecture to product. Responsibilities will include driving system electrical & optical specifications, defining circuit architectures and enabling designs meeting power, performance and cost for next generation optical interconnects. Designs/develops system architectures, defines key capabilities and performance requirements. Develops systems and system element architecture and design and interface definitions. Develops models and architectural guidelines for future system development. Performs analyses at all phases of product development life cycle to include: concept, design, fabrication, test, installation, operation and maintenance. Provides proposal strategy development and review as required. Specify, architect and design low voltage and low power Mixed-Signal integrated circuits from product definition through characterization and qualification. Plan design work with constraints on performance, power, time and quality. Provide guidance to junior designers and layout engineers. Prepare and participate in concept, schematic and final design reviews for circuit blocks. Guidance to develop test plans for lab characterization once design comes back from fab. Document all design work with review materials and detailed design descriptions as well as participate in the writing of datasheets and application notes for customers
The ideal candidate should have 6 + years of experience in high-speed serial links and analog RF IC design and MS in the domain of analog or mixed-signal IC design or equivalent through experience.
Very knowledgeable about the common high-speed serial data protocols NRZ/PAM4 and system standards.
Deep knowledge of analog CMOS/BiCMOS designs in 180nm, 90nm, 45nm and 28nm.
Experience in analyzing link budget for high-speed serial links
Experience with different modulation PAM4/NRZ formats, optical direct detection, coherent detection, and the fundamental digital signal processing
DSP algorithms such as polarization de-multiplexing and clock/carrier recovery, is required.
Deep understanding of RF IC Transceiver architectures, design & tradeoffs
Experience with design of high speed mixed signal circuits e.g., SerDes - analog/DSP based architectures, RX/TX equalization
Experience with design of Analog RF front end circuits such as Drivers, Trans-Impedance Amplifiers TIA, limiting amplifiers, etc.
Good understanding of low noise PLL, Clocking and data recovery architectures.
Deep understanding of Signal Integrity and Channel modeling. Experience in IBIS-AMI modeling of SERDES circuits.
Static timing analysis tools.
Able to create block-level requirements from link budget analysis and models
Good experience in lab testing of high-speed serial links and defining equipment needs
Able to create Verilog-A/AMS behavioral models in Cadence.
Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
Excellent time and task management, and inter-personal skills.Inside this Business Group
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.