Responsible to validate IP I/O Interfaces at IP block and system level. Defines and creates Test Plans for IP RTL Validation develops functional validation tests and running tests across various environments/platforms Simulation, FPGA, Emulation, Silicon in Pre and Post Silicon. Analyzes and debugs failures encountered as well as for future improvements.Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Presilicon Validation teams in improving test content coverage and providing feedback for future ondie debug features.
Degree in Electrical Engineering, Computer Engineering or Computer ScienceExperience with:- C/C++, Python or scripting languages Perl, Ruby, etc.- Validation and debuggingPreferred Qualifications:Experience with:- PC architecture and Intel chipset- Excellent hardware and/or software interfacing skills- Strong analytical mind with problem solving skills- Good planning and communication skills. - Hands-on experience using lab test equipment such as oscilloscopes, logic analyzers and software or kernel debug tools is a plusInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.