RoleIP team is looking for I/O circuit designer responsible for design and development of specialty/Tactical interfaces such as not limited to LVDS, USB, I2C, HSCL, CML, RGMII, GPIO's, HSTL, LVSTL LVCMOS , SSTL, etc. targeted for various SoC's. RequirementsIn depth familiarity with transistor level circuit design - sound CMOS design fundamentalsGood understanding of ESD and LU based design conceptsKnowledge of design for reliability ie. EM, IR, aging, MC etc...Good understanding of layout dependent effects Exposure to scripting for post processing of simulation results PERL, skill etc
PreferredExposure to FinFET technologiesKnowledge of system level budgeting ie. jitter, amplitude, noise, etc...Aware of signal integrity issues ie. effects of packaging, board parasitic, crosstalk, noiseRequires a minimum of Bachelor degree in Electrical or Electronics Engineering with a 3+ years of relevant experience. Resolves a wide range of issues in creative ways. Exercises judgment in selecting methods and techniques to obtain solutions. Contributes to complex aspects of a project. Good communication and interpersonal skills to work closely with the team and interface between other cross-functional teamsInside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.