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Job ID: JR0034325
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type:

Digital Design Engineer

Job Description

Intel is currently developing the Nervana Engine, an application specific integrated circuit (ASIC) that is custom-designed and optimized for deep learning. You will be a key part of a silicon design and verification team chartered with creating silicon IP and ASICs targeted at state of the art Deep Learning and Machine Learning algorithms. Your responsibilities include architecture, RTL design, debug, and support for validation and silicon bringup.


  • Be able to take design from concept to microarchitecture
  • Design RTL/Logic on ASIC, IP blocks or SOCs using Verilog/SystemVerilog
  • Analyze micro-architecture trade-offs and provide clear documentation
  • Simulate and debug logic and deliver high quality designs
  • Support silicon validation and silicon debug

• BS in Electrical or Computer Engineering
• 8+ years of relevant experience in digital design
• Good knowledge in languages relevant to the ASIC development process including Verilog and SystemVerilog
• Experience with scripting in either Perl or Python is preferred


Inside this Business Group

Intel Nervana, leveraging Intel’s world leading position in silicon innovation and proven history in creating the compute standards that power our world, is transforming Artificial Intelligence (AI). Harnessing silicon designed specifically for AI, end-to-end solutions that broadly span from the data center to the edge, and tools that enable customers to quickly deploy and scale up, Intel Nervana is inside AI and leading the next evolution of compute.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
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