A candidate for a temporary position who has not yet graduated and is working towards a relevant Bachelor's, Specialist's, Technical, Master's or PhD degree from a relevant academic institute.The candidates will work on Intel leading edge silicon technologies 10nm, 14nm and 22nm processes. In this position, you will be responsible for physical design layout as part of the Analog High Speed LAN best in class products. You will be responsible for physical design of cell blocks & top level blocks. Experience and/or knowledge of layout methods for analog circuits PLL, IO's, Amplifiers, LDO, ADC, PLL , Etc' will be an advantage. The candidate should know basic concepts on analog design e.g. power rail design, device matching techniques, routing shielding/length matching, Latch Up protection techniques, ESD layout design techniques etc.
Inside this Business Group
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.