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Job ID: JR0011681
Job Category: Engineering
Primary Location: Singapore, Central Singapore SG
Other Locations:
Job Type:

Staff Engineer Physical Design and Logic Synthesis SoC

Job Description


  • Carry out all aspects of logic synthesis, physical design and Timing closure  of complex digital deep sub-micron SoCs.
  • Carry out logic synthesis, scan insertion, create floor plan and power plan, clock tree synthesis, timing driven place and route and static timing analysis to meet area and performance targets.
  • Carry out equivalence check, power analysis, rail analysis, physical verification of design to achieve signoff quality
  • Carry out Layout Verification (ERC, DRC and LVS)

• Master/Bachelor’s Degree in Electronics Engineering • 10+ years of relevant experience • Proficient with cell-based IC design tools, preferably tools from Synopsys galaxy platform. • Chip implementation experience with exposure to SoC partitioning • Proficient in Deep Submicron Technology nodes (layout effects, etc.)

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