SoC Logic Design - Undergrad Intern

Job Description

Role and Responsibilities:

• The Server IP Group is searching for motivated student interns to support Register-Transfer Logic development, using automated methods.
• This person would be working with the test chip development team to improve the efficiency of the Register-Transfer Logic development for test chip components.
• The intern will be exposed to test chip architecture, automation methods currently used for test chip development, and exposure to leading edge hard IPs.
• The intern will also help us in refining our in-house software to accelerate test chip designs.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

Pursuing Bachelor's Degree in Electrical Engineer, Computer Engineering, Computer Science, or a related field.

6+ months of course work in:

• Verilog Register Transfer Language (RTL).

3+ months of experience with:

• Unix shells/Unix commands.
• Scripting in at least one of these languages:  Python or TCL or Perl.

How to Stand out (Preferred Qualifications):

• Experience with hardware functionality, such as state-machines, serial buses, and communication protocols.
• Understanding of GIT, software regression, and quality metrics.
• Create and modify existing scripts.
• Create or understand logic functionalities in terms of block diagrams, data flow diagram, algorithm state machine, finite state machines, and detailed timing charts.
• Experience in addressing LINT, UPF, CDC and Static Timing Analysis issues.
• Perform unit level testing, debug tests, SDC and UPF generation.
• Ensure designs are delivered on time and with the highest quality by using proper checks.
• Work with verification team for test plan/strategy to meet all functional requirements and performance.
• Work with timing and physical team for timing closure and meet power and area goals.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, AZ, Phoenix; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $40,000.00-$108,000.00 (Hourly Role)
*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.