Reliability Verification Technical Manager

Job Description

• As part of the Design Technology Platform Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies, Enablement, Validation and Foundry Certifications of Industry Standard EDA Reliability (EM/IR); ESD Perc tools and drive PDKs towards industry standard methods and ease of use for the end customers.
• The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high quality technology collaterals, models and enablement of EDA tools.
• Direct reporting of Junior Engineers in the team will be involved and the candidate has to first level line manage the people and their deliverables day to day.
• Responsibilities includes:Define technical specification in the area of ASIC IR/EM and PERC ESD domain for Intel advance technology features to enable Intel-specific and industry standard EDA design tools.
• Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders.Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specification.
• Joint effort with partners in DE organization to evaluate and isolate performance contributors for technology features as part of enablement.
• Build and qualify Process Pathfinding Kits and tools with quick turnaround time.Drive innovation and initiatives to enhance existing automation, tools and methodology. Identify and analyse problems, plans, tasks and solutions.
• Cultivate and reinforce appropriate group values, norms and behaviours. Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity.The candidate should also exhibit the following behavioural traits and/or skills: Creative, independent, and out of the box thinker with strong problem-solving skills and analytical ability.
• Experience in driving cross-functional and industry wide initiatives and taskforces.Attention to details, strong organization skills. Depth and Breadth being able to connect the dots and identify cross-discipline optimal solutions.
• Self-motivated, strong leadership skills being able to influence across internal and external ecosystem\Written and verbal communication skills to present complex issues with clarity to drive decisions.
• Able to work with cross-functional and cross site teams and influence multiple internal and external stakeholders. Ability to work in a dynamic and team-oriented environment.

Qualifications

• BS in EE/CS with minimum 10 relevant industry experience OR MS in EE/CS with minimum 8 years relevant industry experience OR Ph.D. in EE/CS with minimum 5-year relevant industry experience in the following areas:
• Minimum 5+ year of people management skill.
• Extensive experience in running all aspects of the IR and EM flows for ASIC designs, must be expert in Ansys RHSC and Cadence Voltus and other In design RV flows and solutions.
• In depth understanding of EM and IR flows methodologies using Ansys RHSC and Cadence Voltus.
• Deep expertise in PERC ESD rule deck development in either Siemens Calibre or Cadence Pegasus or Synopsys ICV rule decks, new process node PDK enablement in PERC ESD space. This includes both Schematic front end design and in back end layout design side of implementation.
• Device level knowledge in ESD operational physics, expertise in modelling lower nm technology ESD complications and new challenging implementation and advancements.-Expertise and multiple years of exposure in implementation or solving Schematic checks, LDL - p2p, CD checks in layout side.
• Planning, execution and validation of Strategic new initiatives in area of PERC ESD implementation, PDK rule decks and new EDA engagements.
• Parasitic Extraction, Device Modelling and Simulation tools/flows.
• Expertise in building testcases, automation to run these EDA tools and interpretation of the results.
• Familiar with Reliability verification in lower nm nodes, EM/IR and ESD concepts, IO cell design and ESD execution.
• Familiarity with TVF, TCL and python automation in deep expertise extent.
• ICV python rule deck implementation expertise is preferred domain area.
• Excellent communication skills, able to clearly articulate the requirements to EDA vendors.
• Project management skills, to effectively and independently own the ASIC RV(EM/IR) tools certification and ESD perc flow methodologies.

Inside this Business Group

Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.