Test Chip Design Integration Engineer

Job Description

Performs integration of cell libraries, functional units, and partitions into subsystems or full chip SoC designs. Conducts the subsystem/full chip layout, integration, verification, and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architectures. Designs, develops, and innovates integration methodologies and flows to improve physical design convergence in domains such as layout, timing, clock tree, formal verification, signal integrity, IO, debug, power routing, noise reduction, reliability, and power and performance. Optimizes design to improve product level parameters such as power, frequency, and area. Collaborates with the design teams during the chip design lifecycle to drive signoff closure for tapeout and meets IP technical and delivery requirements.

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or related field.

Experience above in the following:

- SoC Integration, pre-Si validation, post-Si pattern generation and testing.
- Micro-architecture and design features.
- Behavioral modeling, Verilog/System Verilog coding.
- RTL Synthesis, LEC, Automated Place and Route and Static Timing Analysis.
- UPF (Unified Power Format) validation using low power techniques and handling multiple power domain design.
- Simulation and testing of Analog and Mixed-signal circuits.
- JTAG and other industry-standard protocols, state machines, logic design and verification.

Preferred Qualifications:

Experience above in the following:

- Pre-Si validation - creation of test plan, test bench and test case development, review and debug of test results, and review assertions to prevent illegal states.
- Test bench creation to generate Post-Si test patterns and vectors.
- Scripting languages (perl, tcl etc) to enhance automation in design, validation and testing.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.