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IP Prototyping Engineer Graduate Intern

Folsom, California, Amerika Syarikat ID Pekerjaan JR0259669 Kategori Kerja Intern/Student Mod Kerja Hybrid Tahap Pengalaman Intern Jenis Waktu Bekerja Sepenuh Masa
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Job Description


Role and Responsibilities:

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful.

Your responsibilities may include, but not be limited to:

  • Post-silicon validation graduate intern candidate will be developing test plans and tests, automating tests, executing tests, and debugging failures in pre-silicon emulation and post-silicon environments to validate new product reference designs.
  • Building pre-silicon emulation models.

The ideal candidate should exhibit behavioral traits that indicate:

  • Excellent interpersonal skills, including written, verbal, and presentation communications.
  • Attention to detail and organizational skills.

Applicants for this internship should be able to start between March 2024 and June of 2024 and be available full-time for 6-9 months. This internship will offer schedule flexibility as well as a hybrid work location to allow for classes while completing the internship.


Qualifications


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must be pursuing a Master's degree in Electrical Engineering, Computer Engineering or similar degree OR a PhD in Electrical Engineering, Computer Engineering or similar degree.

  • 3+ months experience with C/C++.
  • Coursework in Computer Architecture and digital design.
  • 3+ months experience with Python.
  • 3+ month experience with debug equipment.

Preferred Qualifications:

  • Experience with debug equipment such as Logic Analyzers and oscilloscopes
  • Knowledge of PCIe, DDR protocols.
  • Previous experience with Post-Silicon validation.

Inside this Business Group


In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Posting Statement


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.



Annual Salary Range for jobs which could be performed in US, California: $63,000.00-$166,000.00
*Salary range dependent on a number of factors including location and experience


Working Model


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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Maggie Offensive Security Researcher

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