Skip to main content

High Speed Serial IO Debug and Validation Engineer

Taipei, Taiwan Job ID JR0225529 Job Category Software Engineering Work Mode Hybrid Experience Level Experienced
Job Description

We are looking for a capable and experienced platform validation and debug engineer with experience in High Speed Serial IO (HSIO) interfaces including PCIe, CXL, etc. This position will help drive our HSIO subsystem validation and debug efforts on our Xeon Platforms, focusing on emerging technologies. You will help lead and deliver platform level quality debug/validation efforts, ensuring a positive experience and end to end solution for our customers. You may be responsible for the development of methodologies, execution of validation plans, and leading the debug of key issues that arise. Requires a good understanding of Serial IO design, implementation and debug on server platforms. May require interfacing with Architecture, Design and Silicon Validation teams and collaboration with team members in other geographic location. Opportunity to work on enabling unique end point devices in the system, including margin testing of those end points, as well as opportunities for influencing performance optimizations on the HSIO interfaces.

In general, you will be one who: Integrates and debugs across the stack for a specific product, platform, feature, or technology throughout the product lifecycle, potentially including pre-silicon development, power on, and/or post-silicon development. Debugs HSIO HW/SW across multiple layers of the stack including firmware, drivers, and operating systems. Develops a debug plan and associated methodologies. Analyzes issues, manages sightings from various validation streams, determines root cause, and drives or develops improvements. Drives project stress and stability and supports power, performance, and key KPI task forces.


Qualifications

Minimum Qualifications: A successful candidate will have a minimum of a B.S. in Electrical Engineering, Computer Engineering, Computer Science or comparable degree w/ 4+ years of experience; or a Masters with a minimum of 3+ yrs of experience; or a PhD w/ 1+ years of experience. 2+ years of platform/lab debug experience.

  • Must have PCI Express validation, debug experience.
  • Must have an solid knowledge of server architecture (or ability to quickly attain such), and understand the High Speed Serial IO links in server designs.
  • Must have an understanding of validation and debug approaches and methods.
  • Must have prior experience testing HSIO / PCIe end point devices in a system environment (may include margin testing, LTSSM testing, etc.)
  • Proficient in Excel.
  • Experience using Intel's ITP debug tools or equivalent.
  • Must be willing to engage with external customers when needed.


Preferred Qualifications:

  • Experience using state of the art debug tools: protocol analyzers, exercisers and/or logic analyzers, O-scope, etc.
  • ucode/pcode experience
  • 2+ year experience in Microcontroller debug experience on CPU/PCH (pre-si and/or post-si) and/or BMC, SPS/ME.
  • Server Platform HW Debug experience.
  • Proficient in Python and ITP usage.
  • Candidates with Electrical Validation background are considerable.

Inside this Business Group
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • Senior BIOS Cloud Engineer Taipei, Taiwan Apply Now
  • BIOS Platform Application Engineer Taipei, Taiwan Apply Now
  • Sr. Serial IO Debug and Validation Engineer Taipei, Taiwan Apply Now
View All Jobs

No jobs have been viewed recently.

View All Jobs

No jobs have been saved.

View All Jobs