Systems Design and Applications Manager
Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person globally, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenges that come with changing the world.
We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.
As a member of Intel's Programmable Solutions Group, you will use your knowledge of Logic Design, Verification, and high-speed IO/SERDES technology to lead a team of experts operating at the system level in enabling customers, both internal and external, to use the Structured ASIC technology. The position requires a self-driven candidate with deep knowledge in design, verification, and communication interfaces, along with excellent communication skills.
Structured ASIC team: This is a structured ASIC team under Intel's PSG and is targeting 5G, cloud computing, and high-end consumer application space. eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.
Responsibilities include but not limited to:
Provide applications leadership to internal and external customer programs pre and post silicon.
Manage/Develop collaterals such as Handbook, Datasheet, and Application notes.
Create protocol specific use models.
Perform protocol specific characterization and author characterization reports.
Work with IP teams and customers to ensure proper usage of the SERDES for various applications and protocols.
Define methodology for high-speed serial IO measurements.
Validate PCS and PMA blocks of the transceiver Leading and dotted line managing the characterization team.
Engage customers to explain current and future SERDES architectures and requirements.
Gather requirements for next generation SERDES and demonstrating technology capability.
Lead the advanced customer support and design win effort as it relates to SERDES Design, Simulation, Bring Up Characterization, and Evaluation Train and provide engineering support to Intel's worldwide customers and Applications team.
Relevant experience can be obtained through work, classes, projects, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
10+ years of relevant experience, experience should include:
Design, development, implementation of FPGAs or ASICs.
SERDES and protocols (such as PCI Express, 10GBASE-KR/SR/MR/ER/LR, 25GBASE-KR, JESD 204X, CPRI/OBSAI, DisplayPort, HDMI, VbyOne or etc.).
Programming and data analysis using Python, Matlab, Perl, C++ or any Object-Oriented language.
SI Concepts, including sources and causes of noise and jitter.
Testing equipment, such as high-speed oscilloscopes BERTs and VNA.
Leading a technical team.
Experience in one (or more) of the following is considered a plus factor
Communication systems theory relating to SERDES.
SERDES IP architecture and implementation.
Analog and digital design.