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SoC Design Engineer Manager

San Jose, California; Santa Clara, California Job ID JR0232951 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.

As a SoC Design Engineer Manager in Intel's Programmable Solutions Group (PSG), you will use your knowledge of Logic Design, Verification, and FPGA technology to lead frontend design, architecture and pre-silicon verification efforts (including IP, integration, and full-chip aspects), both internal and external, to use the Structured ASIC technology. The position requires a self-driven candidate with deep knowledge in design, verification, and communication interfaces, coupled with good communication skills.

Structured ASIC team: This is a structured ASIC team under Intel's PSG targeting 5G, cloud computing, and high-end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.

Areas of responsibility for this role include, but not limited to the following:

  • Be the lead on the overall architecture design, implementation of complex features/flows/protocols, and their interactions with rest of the SoC and with the platform.

  • Own verification of IP integration and/or SoC level flows.

  • Lead the development of the design architecture, logic design, verification strategy, requirements, environments, tools, and methodologies.

  • Apply your knowledge of design methodologies verification principles and techniques and your judgement to drive the team to write architecture specifications, functional and microarchitecture specifications and realize the corresponding RTL designs.

  • Lead the development of test plans, and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.

  • Actively involved in running tests, debugging failures to root cause, and recommending solutions.

  • Collaborate with cross-functional folks to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.


Relevant experience can be obtained through work, classes, projects, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirement

Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

  • 10+ years of relevant experience, experience should include:

  • Frontend design/verification.

  • IP Design Integration (e.g. HSIO, SerDes).

  • Leading a technical team.

  • Scripting languages (e.g. Perl, Python, Shell, etc.).

Preferred Qualifications

Experience in one (or more) of the following is considered a plus factor

  • Functional test vector development and post silicon bring-up/debug.

  • FPGAs or ASICs, SERDES, and networking applications.

  • Analog and digital design.

  • Masters' degree in Electrical Engineering, Electrical Electronics, Computer Engineering or related field.

Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US,Santa Clara

Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here:

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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