SoC Design Engineer Lead
We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.
This is a structured ASIC team under Intel's Programmable Solutions Group (PSG) targeting 5G, cloud computing, and high-end consumer application space. Intel® eASIC™ devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC.
As a SOC Design Engineer Lead, you will use your knowledge of Logic Design, Verification, and FPGA technology to lead pre-silicon verification efforts (including IP, integration, and full-chip aspects), both internal and external, to use the Structured ASIC technology.
The position requires a self-driven candidate with deep knowledge in design, verification, and communication interfaces, coupled with good communication skills.
Areas of responsibility for this role include, but not limited to the following:
Be the lead on the overall architecture design, implementation of complex features/flows/protocols, and their interactions with rest of the SoC and with the platform.
Own verification of IP integration and/or SoC level flows.
Lead the development of the design architecture, logic design, verification strategy, requirements, environments, tools, and methodologies.
Apply your knowledge of design methodologies verification principles and techniques and your judgement to drive the team to write architecture specifications, functional and microarchitecture specifications and realize the corresponding RTL designs.
Lead the development of test plans, and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
Actively involved in running tests, debugging failures to root cause, and recommending solutions.
Collaborate with cross-functional folks to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
Relevant experience can be obtained through work, classes, projects, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
What You’ll Bring (Minimum Qualifications)
7+ years of relevant experience, experience should include:
Design experience (RTL Design, definition, etc.)
Experience in SDC generation, synthesis,
Experience in FPGAs or ASICs, SERDES, and networking applications.
Experience in test plan definition and testcase development in C/Assembly/System Verilog.
Experience in verifying design at RTL level and gate-level simulation.
Experience with scripting languages (e.g., Perl, Python, Shell, etc.)
Ways to Stand Out From the Crowd (Experience in one, or more, of the following preferred qualifications is considered a plus factor):
Experience in analog and digital design.
Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering.
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