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RTL Design and Validation Engineer

San José, Costa Rica Job ID JR0200950 Job Category Engineering Work Mode Experience Level Experienced
Job Description

The Foundational Security team (FST) is looking for digital logic designers and validators keen to work on a scalable IP design. Candidate will be responsible for design and validation of new IP roadmap features as part of FST’s HW IP developing HW security for various market segments across Intel.

As a member of the team, the candidate would be responsible for driving scalable IP development while also making the Design Integration and SOC delivery a fully automated solution. Candidate will be part of an IP team working closely with other verification engineers, RTL design engineers, micro-architects, and other team members in determining the proper implementation strategy for new design, ensure quality of design, and develop test-plans, verification environment, and drive delivery to SoC. They will have an opportunity to learn and contribute towards making Intel Hardware more secure!

Excellent communication and organization skills are critical, along with teamwork, and must demonstrate strong technical skills, along with having passion for design or validation.

Must have strong orientation for Quality and Commit and Deliver and Drive Innovation/efficiencies and have strong strategic thinking to come up w/ paradigm shift solutions to critical design/validation challenges.

Behavioral traits:

  • Strong analysis, debugging skills, and creative in problem solving.


Minimum Qualifications:

The candidate must possess a minimum of bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
2+ years of relevant logic design/pre-silicon verification experience with multiple project cycles.
2+ years of logic design/pre-silicon verification experience with various tools and methodologies including but not limited to:

  • System Verilog
  • OVM / UVM
  • Scripting (Python/Perl/Shell)
  • RTL simulators
  • Interactive debugger
  • RTL model build
  • Testbench development
  • Power-aware simulation
  • Coverage-based random constraint simulation

Capable in developing testplans, tests and verification environment based on High Level Architecture specifications.

Work experience with system Verilog or OVM or UVM or Object-Oriented Programming (OOP)

VLSI or Structural and Physical design flow/methodology experience.

Power management, IOSF, AHB, PCI express or any industry standard BUS protocol experience a plus.

Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here:
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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