Power Modeling Engineer
The mission of Intel’s Programmable Solutions Group (PSG) is to drive the future for Field-Programmable Gate Array (FPGAs) and Structured Application Specific Integrated Circuit (ASICs) technology/solutions around the globe. With the Performance & Power Team, you'll be surrounded by some of the brightest minds in the world as we work across the Programmable Solutions Engineering team to extend our Performance per Watt leadership across all product families and variants.
As a key member of PSG (Programmable Solution Group) Power team, you will be responsible for full chip power analysis and optimization. Responsibilities include power analysis, power model generation and optimization. In this role, you will collaborate closely with cross-functional teams (Design, Planning, Package, Platform) and commit product power to meet business goals. You will also develop flows to enable efficient and accurate power analysis, including workload- and profile-dependent scenarios. If you have a passion for power modeling and optimization, we would love to talk with you.Qualifications
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
BS/MS in Electrical Engineering, Computer Science, or equivalent, with a minimum of 3 years of experience in digital design
3+ years of experience in the following:
Understanding of power model generation and low power techniques
Power analysis tools such as Primetime-PX, Redhawk, Power Artist and Spice
Flow or tool development using Python/Perl/Tcl or C/C++
MS in Electrical Engineering or Computer Engineering with 5+ years of experience
5+ years of experience in power analysis and model generation
Have direct experience on following protocols or domains: DDR, PCIe, Ethernet, HBM
FPGA Experience with FPGA and related EDA tools
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