Director of Engineering
San Jose, California Job ID JR0235692 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job DescriptionIntel PSG is the pioneer of programmable logic solutions, enabling system and semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets. Intel PSG combines the programmable logic technology with software tools, intellectual property, and customer support to provide high-value programmable solutions to many customers worldwide. As Director in PSG's Hardware Engineering group, you will be leading teams with highly skilled managers and engineers that work on next generation IO and memory interfaces. We are looking for leaders who can lead a global team with focus on innovation, execution, and delivering on time with high quality. As Director of IP Development, you will oversee definition, design, verification, and documentation for SoC (System on a Chip) development. Determine architecture design, logic design, and system simulation. Define module interfaces/formats for simulation. Perform Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contribute to the development of multidimensional designs involving the layout of complex integrated circuits. Perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyze equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Select, develop, and evaluate SoC design engineers to ensure the efficient operation of the function.QualificationsMinimum Qualifications BS in Computer Science or Computer Engineering or related field with 12+ years of experience or MS in Computer Science or Computer Engineering with 8+ years of relevant experience , 5+ years of management experience leading teams working on IO and memory interfaces. Preferred Qualifications 10+ years of system level aspects of DDR memory subsystems, configuration / test logic, timing closure, hardware bring-up and debugging. FPGA chip design experience.Inside this Business GroupThe Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.Covid StatementIntel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.htmlWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.