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SoC Backend Design Engineer

Phoenix, Arizona; Hillsboro, Oregon; Santa Clara, California Job ID JR0229721 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description

Performs all aspects of SoC design flow from synthesis back, place and route, timing and power all the way to tape-out to create a design database that is ready for manufacturing. The focus of these designs is test-chips for high-speed CPU implementation.
This includes:

  • Power/Performance/Area (PPA) trade-offs to achieve optimized designs.
  • Floorplanning including trade-offs in the form of memory macro placements, power grid definition, and integration requirements.
  • Performs Design Rule Check (DRC), Layout vs. Schematic (LVS) and post-synthesis validation activities.
  • Implementation of Design-for-Test (DFT) features such as SCAN, MBIST, JTAG, etc.
  • Formal Verification and Gate Level Simulation to achieve complete design coverage.

About the team:
You'll be part of Advanced Design (AD) within Design Enablement organization (DE). The team works in close collaboration with our partners in process technology and design teams spanning CPU, Graphics, Networking, and Servers. The primary focus of the team is to accurately predict the impact of process changes on density scaling and power, performance metrics through Test Chips. Test chips are based on both Intel IP and external industry standard IP.


Qualifications

Minimum requirements:
BS in Electrical Engineering with 4 or more years of professional work experience
Or MS in Electrical Engineering or Computer Engineering with 2 or more years of professional work experience.
Work experience must be in the following areas:

  • Experience with the RTL design flow from synthesis to GDSII
  • Design for Test (DFT) elements (Scan, JTAG, MBIST, JTAG or debug technologies)
  • Synopsys or Cadence design (RTL to GDS) tools and flows, including Primetime


Preferred:

  • RTL/Logic design Verilog, VCS, etc.
  • Python, Perl or TCL/Tk programming
  • ICV or Calibre DRC/LVS for layout cleanup

Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US,OR,Hillsboro;US,CA,Santa Clara


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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Maggie Offensive Security Researcher

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