Returnship - Design Enablement
Have you taken a career break and had your resume rejected because of your resume gap? Intel is offering 16-week paid returnships for experienced professionals ready to return to the workforce.
If you have taken a break of at least one year for the following reasons we welcome, you to apply:
- Starting or raising a family
- Military service/military spouse
- Community service/volunteer work
- Caring for a family member or self
At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. This program offers you a chance to revamp your skills, update your resume with new experience, and make connections with others transitioning back to the workforce.
This position is hybrid during the 16-week returnship program. The goal of this program is to hire individuals who were successful throughout the program duration. A full-time offer will be hybrid.
By applying to this posting your resume and profile will become visible to Intel's Recruiting team, and will allow them to consider you for current/future job openings aligned with the skills and positions listed below. You'll be considered for multiple roles within the Design Enablement team of our Technology Development Organization.
Responsibilities may be quite diverse and are technical in nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job.
- Candidates must have been out of the paid workforce for at least one year.
- Bachelors or Master's degree in Electrical Engineering, Computer Science, Computer Engineering or related field with Industry experience in at least one the following areas:
- Foundry design rules and layout concepts on advanced process nodes
- Experience with layout and layout tools on chips
- Design rule checking (DRC) and Layout vs Schematic (LVS)
- Familiarity with scripting or programming languages, such Perl, Python, TCL
- Analog Circuit Design
- Device physics
- DRC/LVS/Extraction runsets
- Custom or ASIC layout design
- CMOS silicon process technology OR VLSI design.
- EDA Tools: Cadence Virtuoso or Custom Compiler