Packaging Research and Development Engineer
Assembly and Test Technology Development (ATTD) Microelectronic Packaging Engineers provide package design, project management, and development-sustaining support for integrated circuits, semiconductor assemblies, and various other electronic components and/or completed units.
Responsible for the thermal and/or mechanical and/or electrical design analysis and development of electronic packages. Package Design Engineer defines the overall package performance and specification and realizes technology certification boundary through product package and/or test vehicle layout design. Conducts tests and research on basic materials and properties. Establishes material specifications for contract assemblers and raw material vendors and interfaces with Quality Assurance and Purchasing regarding material quality and vendor performance. Provides consultation concerning packaging problems and improvements in the packaging process. Communicates and responds to customer requests and participates in customer engaging events as they occur. Develops solutions to problems utilizing formal education and judgment.
The candidate should also exhibit the following behavioral traits and skills:
Team player with experience collaborating with customers
Communication and stakeholder management skills
This position requires US citizenship and is not eligible for Intel immigration sponsorship.
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Possess a Bachelor's Degree with 4+ years of experience or Master's degree with 3+ years of experience in Electrical Engineering or Mechanical Engineering or related discipline.
2 + years experience with microelectronic package or PCB physical layout design using package design tools such as Mentor Graphics Xpedition, Cadence Allegro, or AutoCAD.
Hands-on experience performing package I/O routing and device power delivery studies starting day 1.
Demonstrate to pursue several what-if scenarios regarding I/O routing and/or power delivery strategies with minimal oversight and directions.
Experience in microelectronic package substrate technology development.
Experience and/or familiarity with Intel pacakge design tools such as Package Layout Automation (PLA) and FIELD.
Experience with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS. Ability to extract signal integrity and/or power delivery electrical models and run AC/DC/Frequency Domain simulations.
Experience with scripting using Python, VB, C, and or other languages.