SoC Logic Design Engineer
Devices Development Group Malaysia (DDG-MYS) Client SOC Team is looking for highly passionate new talents to work on Intel’s next generation Client SOC development as a SOC RTL/Logic Staff Design Engineer.
Your will be contributing to the latest Intel Client family of products, be the brain behind the best brain and create the world-changing technology that makes it into the hands of the world’s population!
You will be responsible for
- DDG internal IP RTL design/development OR high performance/bandwidth IP integration into SOC.
- Define and implement new features, change requests/improvements on existing features for the IP.
- Drive and ensure IP-SOC handoff quality assurance and compliance.
- Perform logic/RTL integration into SOC, define power intent strategy, handling of signals crossing power planes and clock domains; along with other FE collateral for system/software integrations.
- Perform design exercise, collaborate with verification team for functional/feature/integration validation.
- Perform FE Quality checks in various logic design aspect ranging from RTL static checks to RTL synthesizability check, timing/power convergence, netlist quality check, Formal Equivalent Verification and many more.
- Candidates should have a minimum of a Bachelor or Master Degree in Electrical & Electronic or Computer Science Engineering with at least 3 years working experiences in IP or SOC RTL/Logic Design.
- Knowledge in one or more of the following domains:
- IP/Subsystem architecture, I/O architecture, industry standard high speed bus protocols
- Industry exposure and knowledge of SoC/ASIC design methodology
- SOC fabric and interconnect design
- Proficient in RTL design using Verilog/System Verilog
- Knowledge in industry FE/RTL tools and design methodologies
- Experience with scripting/firmware/system-software development
- Experience with pre or Post-Si lab debug/power on
- Excellent communication and collaboration skills and a strong team player