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SoC Design Engineering Graduate Trainee

Malaysia Job ID JR0232747 Job Category Intern/Student Work Mode Hybrid Experience Level Intern
Job Description
Are you looking for a fulfilling career as a digital design engineer working on leading edge technology in a world class company? Does solving complex issues that utilize and develop your technical skills in a challenging environment as part of a diverse and talented team make your heart race? Do you wish to make a difference and know that your contribution continuously enriches the lives of the people around you? If this sounds like you, we welcome you to join us as an DFx Design Engineer of Malaysia Design departmentWe're looking for you to: Utilize your competency and talents in DFT, JTAG and industry standard debug protocols as well as high speed I/O design and protocols (such as SATA, PCIe) to design, implement and verify IPs that are used in broad ranging products including next generation servers, SoCs, tablets, smartphones, desktops and Ultrabooks. This includes understanding architecture specifications, RTL implementation, block level verification, integration of IPs, executing integration flows, leading debug activities as well as timing convergence, ECO implementation and associated ASIC tasks. Grow into the technical expert and collaborate closely with cross functional teams in delivering a Best in Class IP that is area and power optimized on challenging schedules. You will be given the challenge of producing reusable designs that meets performance as well as low power requirements on the latest 14nm and the upcoming 10nm process technology that are 2-3 generations ahead of the industry. This will require you to work closely not only with the digital design team; but also with the analog and structural design team in identifying the best design that meets these goals. Support various product teams in integrating the IP that has differing requirements and usage models. You will have an opportunity to collaborate with geo-diverse teams in analyzing, debugging and identifying the root cause of issues that arise from complex design development. We look forward to your innovative recommendations that will resolve the identified issue that accounts for technical and project constraints/requirements. This will include a time based plan of action. Continuously learn, master and improve the current design, integration as well as validation activities that forms the ASIC flow via automation, scripting, fresh ideas and unconventional thinking.
Qualifications
Qualify with Bachelor/Master degree in (Electrical and Electronics or Computer System). Good knowledge in RTL integration and validation methodologies, preference given to those good in Verilog and C programming.Enjoy pick up protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe. Best match if you do have knowledge in HVM, DFX, scan, JTAG and debug functionality. Genuine curiosity into microprocessors, computer system architecture and high speed design as well as producer consumer transactions. Also dedicated and proficient in digital state machine architecture and logic design.Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows If you obtain below personality..Enjoys tinkering and teamwork to arrive at solutions to critical problems. Treat obstacles as opportunity and always stay positive. Great in communication and be able to work in different type of people.Please, apply the job, that's you.
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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