Skip to main content

PVT and Timing Methodology Technical Lead

Malaysia; Bengaluru, India Job ID JR0234529 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description

The mission of Intel's Programmable Solutions Group (PSG) is to drive the future for FPGAs and Structured ASICs technology/solutions around the globe. With the Performance and Power Team, you'll be surrounded by some of the brightest minds in the world as we work across the Programmable Solutions Engineering team to extend our Performance per Watt leadership across all product families and variants.

As a PVT and Timing Methodology Technical Lead, you will have the following responsibilities:

  • Define PVT corners for optimal PPA for all FPGA, SOC and ASIC products.
  • Define and drive design signoff methodology for standard cell, custom and analog design styles.
  • Define and minimize design timing guard band, accounting for affects such as aging and OCV.
  • Collaborate with manufacturing teams to adjust guard band based on post-silicon data.
  • Collaborate with the cross-functional teams to tackle new challenges in latest process technology nodes, for efficient design implementation and execution.

The ideal candidate should exhibit the following behavioral traits: Strong communication skills and attention to detail are essential for success in this role.


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education:

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum Qualifications:
  • 5+ years of experience in SoC design closure.


Preferred Qualifications:

  • Knowledgeable with device physics and circuit simulation.
  • Familiarity with EDA tools like DC, Primetime, Spice, Cadence, etc.
  • Master's Degree in Electrical Engineering, Computer Engineering, or related field.
  • Programming language: C++, C sharp, Python, etc.
  • Experience with timing and power related Silicon correlation.
  • Familiarity with FPGA design tools such a Quartus or Vivado.
  • Willing to work with different time zone functional team (India/US/MY)
  • Flexibility and independency working environment.
  • Individual contributor role and working with regional team.

In this role, you will be one of the decision making among the teams by influencing and affecting others to create a better product. You will also involving with multiple Intel product and latest Intel technology.


Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

IN,Bangalore


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • SoC Designer Multiple Locations Apply Now
  • Tester Equipment Development Engineer Multiple Locations Apply Now
  • Senior DFT Engineer Malaysia Apply Now
View All Jobs

No jobs have been viewed recently.

View All Jobs

No jobs have been saved.

View All Jobs