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ASIC PD implementation lead engineer

Hyderabad, India Job ID JR0230824 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description
As a part of the PDK validation team, candidate will work on ASIC block implementation and timing closure of chosen test blocks for PDK validation on both Synopsys and Cadence flows, on specific Intel process technologies. Flows (Synthesis, APR, Timing, LV and RV) have to be evaluated on set QoR criteria and cross EDA flow benchmarking needs to be done and the results need to be published in a standard format for each kit. In Integration QA, a mini-full chip die needs to be assembled using the above ASIC blocks, memories, IOs and QoR published. Should be able to technically guide a team of 4-5 team members and review their work. Ability to help debug complex design and flow issues is needed. Timely reporting and tracking of issues to full resolution is a core part of the job.
Qualifications
BTech/BE/MTech/ME/MSc in Electronics/Computer science with 8 yrs Industry experience in ASIC design implementations and timing closure. Hands-on experience with Place and Route tools, Timing tools, Floor planning, IR Drop and Physical verification. Should have good understanding of Verilog/VHDL, exposure to low power techniques and PPA analysis. Knowledge of tcl and perl scripting is a plus. Strong organization, presentation and communication skills within an international environment. Good in stakeholder management and should be detailed oriented.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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