Xeon SoC Structural Design Intern - Graduate
In this internship, you will be working alongside a world-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon products/IPs for Server markets.
Your responsibilities will include but not be limited to:
- Block-level floor planningLogic synthesis of design blocks
- Formal Equivalence Verification FEV
- Auto Place-and-Route APR using Synopsys ICC tools
- Timing verification using Synopsys PrimeTime as well as Intel tools
- Physical verification
- Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM
- Assist in the preparation of the layout design database for introduction to manufacturing
- Willingness to commit to a 6-9 month internship
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Candidate must be pursuing a Master's degree in Electrical Engineer, Computer Engineering, or related field - OR- pursuing a PhD in Electrical Engineer, Computer Engineering, or related field.
3+ months of experience in:
- Coursework and/or project work with CMOS transistor level circuit fundamentals, VLSI hardware design, and programming
- RTL/Logic design Verilog, VCS, etc.
- Electronic Design Automation tools, flows and methodology
- ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog
- Layout cleanup expertise DRCs, density, ipc, etc.
- Circuit design
- Computer architecture
- TCL, Perl and/or C++ programming
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