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Xeon SoC Structural Design Intern - Graduate

Hudson, Massachusetts; ; Remote Job ID JR0235590 Job Category Intern/Student Work Mode Hybrid Experience Level Intern
Job Description

In this internship, you will be working alongside a world-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon products/IPs for Server markets.

Your responsibilities will include but not be limited to:

  • Block-level floor planningLogic synthesis of design blocks
  • Formal Equivalence Verification FEV
  • Auto Place-and-Route APR using Synopsys ICC tools
  • Timing verification using Synopsys PrimeTime as well as Intel tools
  • Physical verification
  • Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Manufacturability checks DFM
  • Assist in the preparation of the layout design database for introduction to manufacturing
  • Willingness to commit to a 6-9 month internship

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must be pursuing a Master's degree in Electrical Engineer, Computer Engineering, or related field - OR- pursuing a PhD in Electrical Engineer, Computer Engineering, or related field.

3+ months of experience in:

  • Coursework and/or project work with CMOS transistor level circuit fundamentals, VLSI hardware design, and programming


Preferred Qualifications:

  • RTL/Logic design Verilog, VCS, etc.
  • Electronic Design Automation tools, flows and methodology
  • ICCDP, Design Compiler, IC Compiler/ICC, Primetime, VCS, Verilog
  • Layout cleanup expertise DRCs, density, ipc, etc.
  • Circuit design
  • Computer architecture
  • TCL, Perl and/or C++ programming

Inside this Business Group
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US,Virtual


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in US, Colorado:$52,000.00-$147,000.00

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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