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SOC DFx Design Engineer

Ho Chi Minh City, Vietnam Job ID JR0221184 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description

Seize the opportunity to work with the team responsible for providing technical leadership in the development of high quality and feature rich chipset products for PCs millions of people around the world will use. As part of the global Chipsets Silicon Group (CSG) within Silicon Engineering Group, you will be responsible for the Design-for-X (Test, Debug, Manufacturing) definition, implementation and verification for Chipset products.

As a Chipsets System on a Chip (SoC) DFx Design Engineer, a typical day may include, but is not limited to:
DFx Scan Design Engineer

  • Overseeing the Scan/ATPG definition, design, verification, and documentation for SoC development.
  • Determining Scan architecture design, logic design, and system simulation.
  • Defining module interfaces/formats for simulation.
  • Performing logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, RTL coding, and SoC simulation.
  • Contributing to the development of multidimensional designs involving the layout of complex integrated circuits.
  • Performing all aspects of the SoC design Scan flow such as coverage analysis, setup and debug Spyglass-DFT or other ATPG tools, generate ATPG patterns via Mentor Graphic Tessent or other equivalent tools, RTL and GLS test validation to ensure quality design, debug and root cause stuckat and atspeed failure using Mentor GLS testbench in Synopsys VCS tools, and validate chain test in serial testbench.
  • Driving post-Silicon High Volume Manufacturing (HVM) Team partnership to enable Scan DFT test capability.
  • Collaborating with various stakeholders in architecture, IP, structural design, SoC RTL, and post-Silicon teams.
  • Reviewing vendor capability to support development.

DFx Micro-Architect

  • Drive product early technical readiness (TR), which require to understand customer requirement and plan for design definition solution.
  • Close handshake with DFx RTL design and Pre-Silicon Verification team to ensure quality of DFx feature implementation.
  • Knowledge and hands-on experience on peripheral protocols such as I/O design protocols (SATA, PCIe, USB and others) is an added advantage.

DFx RTL Design Engineer

  • Perform DFx logic design RTL coding and integration into the Chipset SoC.
  • Review and fix the DFx logic design to ensure all signal/clock connection, timing and etc. meet the design specifications with zero design errors.
  • Knowledge and hands-on experience on MemoryBIST design is an added advantage.
  • Strong communication skill to collaborate with geo-diverse teams (IP, SoC, Structural Design, IP, post-Silicon manufacturing) to analyze, debug, root cause and fix all DFx design issues.

DFx Pre-silicon Verification Engineer

  • Understand Design-for-Debug (DFD), Design-for-Test (DFT), Design-for-Manufacturing (DFM) or Design-for-Verification (DFV) features through design specs.
  • Develop and document test plan and test sources. Ensure all the RTL Design being validated well to eliminate design flawless to customer.
  • Perform test verification and enhancement to ensure design quality and robustness.
  • Drive test review with counterparts such as Pre-Silicon SoC, IP design, Post-Silicon Manufacturing, Board Design and other teams.
  • Take ownership and partner with Manufacturing and Verification team to enable the post-Silicon defect screening, burn-in and system validation.
  • Knowledge and hands-on experience on DFx test environment is an added advantage.

You are:

  • An excellent communicator
  • Extremely organized
  • A team player who loves to collaborate
  • A strong technical leader who communicates well with great influencing skills
  • Passionate for design/tools and methodology
  • Someone who meets their commitments
  • Motivated
  • Self-driven
  • Someone who wants to make a difference through technology

We are:

  • Open to new ideas and methodologies
  • A collaborative team demonstrating the best teamwork across Intel
  • Here to help you succeed
  • People who want to do innovative things

If your skillsets align with our needs, we will provide you a great path to maximize your positive impact on the world.

  • Bachelor/Master of Engineering or Science degree in Electronic, Electrical, Computer Engineering or any related field.

Fresh or less than 15 years of working experience.

Additional qualifications include:

  • Familiar with UNIX, and well-versed in Verilog or C Programming.
  • Knowledge in RTL integration and verification methodologies.
  • Knowledge in Design-for-X (DFx), where X is Test (DFT), Debug (DFD), Manufacturing (DFM) or Verification (DFV).
  • Familiar with Scan design, methodology, coverage analysis and test verification.
  • Ability to communicate well with counterparts and key stakeholders including cross-site partners.

Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here:

Your privacy matters to Intel and we comply with applicable data protection laws. We collect and maintain personal information for recruitment related activities and your data will not be used for any other purpose. We retain personal information for the periods and purposes set forth in Intel Privacy Notice. Retention periods can vary significantly based on the type of information and how it is used. We do not share your personal information with third parties. In order for Intel to communicate with you on your application results, by submitting your information and proceeding with this application, you agree and consent that we can collect your personal information. You will have the ability to opt-out by informing or at any time selecting unsubscribe found at the bottom of our future marketing communications. You have rights to correct, update, request access to or deletion of your personal information as described in Intel Privacy Notice. In addition, if you wish to update or otherwise make changes to your resume, use Intel online application tool to resubmit a new resume.

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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