SOC Design Engineer - Physical Design - Returnship
Have you taken a career break and are now interested in returning to the workforce? Intel is offering a 20-week paid returnship for experienced professionals ready to return to the workforce. If you have at least 5 years of professional experience and have taken a career break for 2+ years for any of the following, but not limited to reasons, we welcome you to apply:
Starting or raising a family
Military service/military spouse
Community service/volunteer work
Caring for a family member or self
At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. Through this program you will have the opportunity to revamp your skills, update your resume with new skills and experiences as well as make connections with others transitioning back into the workforce.
This position is hybrid at the Hillsboro OR site during the 16-week returnship program.
Come join Intel's Client Engineering Group responsible for designing Client SoCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptops and desktop computers We are looking for an SoC System on Chip Physical Design Engineer ready to research design develop and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry.
This role is within Intel's highly regarded Devices Development Group headquartered in Oregon with additional sites in Texas and Malaysia. Our bold purpose as a company is to create world changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.
Your responsibilities may include but not be limited to:
Drive performance optimization including co optimization work with process teams to create best in class designs.
Physical synthesis place and route and clock tree synthesis with Synopsys or Cadence tools.
Static timing analysis constraint understanding generation clock stamping and timing closure.
Multiple Power Domain analysis using standard Power Formats UPF or CPF.
In addition to the qualifications listed below the ideal candidate will also demonstrate the following traits:
Self-motivator with solid problem-solving skills.
Leadership skills with willingness to mentor junior designers.
Willingness to work with teams across project domains and geos.
This position is not eligible for Intel immigration sponsorship
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 3+ years' experience; OR a Master's degree in Electrical or Computer Engineering or a related field and 1+ years' experience ; OR a PhD in Electrical or Computer Engineering or a related field
Candidates must have taken a career break for 2 or more years.
Experience in backend physical design and/or integration.
No jobs have been viewed recently.View All Jobs
No jobs have been saved.View All Jobs