Pre-Silicon Validation Engineer
Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 8+ years of experience -OR- a Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience in:
Test bench development using UVM or analogous methodologies.
Developing Scoreboards and stimulus generators for complex blocks.
C/C++ and interpreted Python languages.
Unit/module ownership throughout the project lifecycle.
Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems
Intel Architecture ISA and system architecture, x86 assembly language is a plus.
Strong domain knowledge of computer architecture.
Industry experience validating Out-of-Order execution, Branch prediction or float point is preferred.
Post-silicon validation experience using System Verilog verification development experience.
Experience in leading/mentoring other engineers.
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