Pre-Silicon Validation Engineer
The world is transforming - and so is Intel! Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth.
We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible.
The Advanced Architecture Development Group (AADG) is a CPU Core development team primarily located in Portland, Oregon. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we invite you to join us, to do something wonderful!
The focus of this role is to be part of a team of pre-silicon verification engineers to verify new and existing features for Intel's next generation CPU IP resulting in bug free final design.
You will be responsible for exhaustively validating the RTL implementation of new architecture and microarchitecture capabilities using a combination of standalone and top level test environments as well as formal verification.
Role responsibilities include although not limited to:
Technical ownership of verification of a microarchitecture block methodology or otherwise significant aspect of CPU validation.
Collaborate with architects hardware engineers and ucode engineers to understand the new features being implemented.
Read and interpret technical specs and create high quality technical documentation like test plans strategy documents and coverage plans.
Plan and implement the UVM test-bench functional coverage model and assertions.
Developing validation content like tools test generators to match the complexity of new cores and be reused in pre-si and post-si.
Participate in debugging failing verification tests to determine if the root cause is an error in the RTL verification model or the test.
Fix all identified failures in the verification model Investigating new techniques to accelerate validation of CPU hardware
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must have a Masters or PhD degree in Electrical or Computer Engineering with 3+ months of experience in:
CPU or ASIC verification
Programming in CC for modeling and assembly language programming
Assertion and Functional Coverage
Debugging RTL code using simulation tools
Verilog System Verilog
Exposure with OVM UVM
Projects or internship in CPU or ASIC verification and functional modeling
Experience with scripting languages like Python/Perl
Relevant courses Computer Architecture Digital Design Verification
Logic Design Programming Languages Data Structures
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