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PPA Structural Design Engineer

Hillsboro, Oregon Job ID JR0228934 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description

About the role:
As part of Advanced Design (AD) team within Design Enablement (DE) organization, you'll work on Design and Technology Co-Optimization (DTCO) to solve unique challenges in close collaboration with various partners from technology development to design teams spanning Client, Graphics, Networking, Servers, and FPGA. The primary focus of the team is to accurately predict power, performance, and area (PPA) through physical design to facilitate data-driven decisions to define future Intel process technologies.

Your responsibilities will include one or more of the following,

  • Perform block PPA including RTL synthesis, floorplanning, clock tree synthesis (CTS), place and route (PnR), and sign-off on various Intel products within their constraints
  • Optimize for best-in-class PPA through TFM and process technology features by working with EDA vendors and Technology Development (TD) teams
  • Understand leading edge processes intricacies and PPA trade-off to benchmark high performance, high density, or low power for bottlenecks and make design and technology recommendations
  • Leverage automations and explore new design optimize techniques including machine learning to drive quality and reduce turnaround time

About our organization:
You will be part of Intel's Advanced Design (AD) organization housed within the larger Design Enablement (DE) team that is focused on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits to enable best-in-class Foundational IP collateral and product design across all generations of Intel process technology. Join Intel and build a better tomorrow. At Intel you can help build computing technology to connect and enrich the lives of every person on Earth.


Minimum Qualifications:
Master's degree in Electrical or Computer Engineering or related discipline with 2+ years of professional experience in the following areas:

  • ASIC design flow including RTL synthesis, floorplanning, clock methodologies, place and route, power and timing sign-offs, device physics, and PPA trade-off
  • EDA tools such as Synopsys Design Compiler, IC Compiler, or Cadence Innovus
  • At least one of the following scripting languages: Python, TCL, or Shell

Preferred Qualifications:

  • Industry experience of low-power and high-performance optimizations, and PPA trade-offs
  • Experience in Graphics SoC design and architectures

Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here:

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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