Power Management Verification Engineer
The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. The Advanced Architecture Development Group (AADG) is a CPU Core development team.
We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible.
If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we invite you join us, to do something wonderful!
Validation of a Power Management IP or feature, either directly or at the system level.
Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware, and other tests as a guide
Learning the architecture, microarchitecture, and Power Management flows by debugging failures to the root cause
Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution
Developing tools and methods to streamline PM IP development, PM HW/FW integration, and SOC integration to deliver highest quality design in shortest time possible
Developing debug tools and validation software
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have either a BS + 5 years' experience or MS + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
Minimum 3 years' experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
Minimum 3 years' experience working on Power Management IP, PM Firmware, or PM SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM.
Minimum 3 years' experience with writing validation plans and software to implement those validation plans.
Minimum 1 year experience with UNIX or Linux.
Minimum 1 year experience with Power Management computer architecture.
Minimum 1 year experience with Python, C++ and/or Verilog programming experience.
Minimum 3 years' experience with validation or testing experience, especially in a silicon design team.