Novel Memory Circuit and IP Design
We're looking for Novel Memory Circuit and IP Designers. This is a very dynamic and innovative position where the designed emerging memory arrays are used for both technology development and future novel Product IPs.
About the role:
Job requires schematic drawing, pre and post layout Spice simulations, Timing validation using tools such as Primetime. It also requires validating the design for Electro Migration, and transistor Aging. Experience in Memory IP Delivery is a plus, such as generating .Lib files with Power attributes etc. for customer integration.
About our organization:
Advanced Design (AD) Group under Design Enablement in Technology Development has primary focus of Design Technology and Foundational IP development to support both the Technology Development organization and Intel's IP/Product design teams. Results of our innovative, high-quality and exciting memory design and development work are published at prestigious conferences and journals, as well as many patents issued.
Following are few examples of these publications from our group:
Liqiong Wei et al., A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique, ISSCC Dig. Tech. Papers, Feb. 2019.
Pulkit Jain et al., A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V, ISSCC Dig. Tech. Papers, Feb. 2019.
Fatih Hamzaoglu et al., A 1Gb 128GB/s Bandwidth Embedded DRAM in 22nm Tri-Gate CMOS Technology, IEEE J. Solid-State Circuits, pp. 150-157, Jan. 2015
Mesut Meterelliyoz et. al., 2nd Generation Embedded DRAM with 4X Lower Self Refresh Power in 22nm Tri-Gate CMOS Technology, IEEE Symp. VLSI Circuits, June 2014
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
The experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
MS degree in EE or related field with 2+ years of professional/ work experience OR
PhD degree in EE or related field with academic work experience.
Experience in the following:
Custom circuit design
EDA Timing, Schematic, Layout and RV tools
Memory IP Delivery, If candidate has owned delivering SRAM or Register File IP Collaterals to Customers
Memory Circuit and IP Design
RTL and synthesis of digital blocks.
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