Logic Design and Pre-silicon Verification Engineer
As a member of the logic design and pre-silicon verification team within the Lead Vehicle Development (LVD) group you will be part of Intel's larger Design Enablement (DE) organization.
You will be a leader on a team that develops the RTL models and pre-silicon verification tests for test chips on next-generation silicon manufacturing processes.
Your responsibilities will include:
- Creation of pre-silicon verification test plans, formal verification, SystemVerilog UVM testbenches and verification test cases
- Creating new digital, analog, and mixed-signal RTL models for new and existing designs
- Running the functional equivalence verification (FEV) flow to compare RTL to schematics
- Delivering RTL design of new and existing digital systems ranging from design-for-test (DFT) to novel designs that enable Power-Performance-Area (PPA) studies on next-generation process technology nodes.
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field of study and 1+ years of Academic or professional experience in the areas listed below
- You must already have a Bachelor's degree, or expect to have one, by December 2022 OR a Master's in Electrical Engineering, Computer Engineering, or related field of study AND 6+ months of Academic or professional experience in the areas listed below
Academic or professional experience must be in the following areas:
- RTL design using Verilog or SystemVerilog
- Pre-silicon logic verification using SystemVerilog
- Knowledge of OVM/UVM test bench development and verification concepts
- SystemVerilog Assertions (SVA), their creation and application in closing verification coverage
- Object Oriented Programing (OOP)
- Coverage driven verification
- Experience with analog and mixed-signal circuits
- Experience in the Unified Power Format (UPF) specification
- Experience with scripting and automation languages such as Python, Perl, Tcl, et. al.
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