CAD Software Engineer
As a CAD Software Engineer in the Lead Vehicle (Test Chip) Development group, you will be responsible for the development of physical design automation tools, flows, methodologies, and processes to support design of Intel's next generation process technology and yield test chips.
Your responsibilities include, but are not limited to:
- Development of EDA software tools and flows that automate generation of E-Test structure devices, routing, layout dummification, and physical design verification
- Development of Design Rule Check (DRC) run-set software to implement test structure process design rules
- Development and support of test chip layout library for the latest process nodes
- Collaborating with semiconductor process technologists to define test structure designs
- Troubleshoot design and DRC verification issues with complex physical design flows and tools
About the team and organization:
Intel's Lead Vehicle Development (LVD) Team is one component of the larger Design Enablement (DE) organization, that provides design and manufacturing services to a variety of internal and external customers who leverage Intel's holistic design and manufacturing expertise to deliver unique circuits and systems at the leading edge of the technology curve. LVD's mission is to develop test-chips and other hardware prototypes that enable our customers to use Intel's most advanced process technologies to develop innovative products and reduce their time-to-market.Qualifications
- Master's OR Ph.D. degree in Electrical Engineering (EE or ECE or ECSE), Computer Engineer (CE), Computer Science (CS), or related engineering discipline
- 6+ months experience in the following at graduate school research, projects or from previous jobs: Programming and scripting languages such as Python, Tcl, or C++; Working with UNIX/Linux computer platforms.
- Experience with industry standard EDA tools such as Cadence Virtuoso, Synopsys ICV, Siemens Calibre for use in physical design, place and route scripts, and DRC verification
- Development of parameterized cells (PCells using Cadence SKILL) or PyCell.
- Understanding of layout design rules, CMOS physical layout design, VLSI test circuits, device physics and semiconductor processing.
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