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CAD Research Intern

Hillsboro, Oregon Job ID JR0235806 Job Category Intern/Student Work Mode Hybrid Experience Level Intern
Job Description

As a CAD Research Intern in the Design Enablement Test Chip Engineering (TCE) group, you will be responsible for the research and development of CAD software tools and flows, methodologies, and processes to support the design of Intel's next generation process technology test chips.

Your responsibilities will include but not be limited to:

  • Development of CAD software/flows that automate physical layout of E-Test Structure devices and connectivity, layout dummification, design verification within a customized physical design framework
  • Definition of process design rules to make designs conform to process requirements
  • Collaborating with other manufacturing groups to define test structure designs
  • Troubleshoot design and DRC verification issues with complex physical designs flows and tools
  • Develop software to increase automation and productivity
  • The candidate is expected to work closely with the team but carry out research, development, and test tasks with minimal supervision

This is an internship position and compensation will be given accordingly. This is a 3-6 month internship.


Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

  • Pursuing a Masters or Ph.D. degree in Electrical, Computer science, or other related engineering discipline
  • 6+ months of experience in following areas:
  • One of the following: Python, Perl, Tcl, SKILL, C++
  • Solving problems using efficient computer algorithm and effective programming techniques
  • UNIX/Linux or Shell
  • Experience with industry standard CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.


Preferred Qualifications:

  • A Ph.D. candidate with research experience in physical design or CAD
  • Experience in development of PCells or PyCells
  • Experience in Calibre SVRF and/or Cadence SKILL languages
  • Experience in developing custom flows for EDA Tools using AI/ML concepts
  • Semiconductor device physics and process scaling

Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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