Advanced Digital SoC Design Integration Engineer
In this role you will be part of the Advanced Design Team (AD) which is focused on pathfinding and development of advanced memory and circuit design technologies that enable best-in-class memory collateral and IP that are implemented in product designs across all generations of Intel's process technologies.
About the team:
AD resides within Intel's larger Design Enablement (DE) organization, which offers a broad scope of design and foundry services to internal and external partners. At Intel, DE is a key pillar enabling the rapid delivery of products to the marketplace that push the envelope of what is possible in SoC and computer hardware design. Your work in this integrated environment will directly enable design teams to not just develop innovative technologies, but to deliver them ahead of the competition and with the same quality Intel is known for and the market demands.
You will oversee definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.Qualifications
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required, but may give you an advantage in the interview process.
Bachelor's Degree in Electrical and/or Computer Engineering with 2 + years of professional work experience.
Master's Degree in Electrical Engineering and/or Computer Engineering
Ph.D. in the same disciplines.
Experience must be in the following areas:
ASIC design flow from synthesis to tape-out
Reading and understanding RTL functionality
EDA tools and flows using Cadence or Synopsys for digital SoC design
At least one of the two following: SPICE simulation or RTL validation
Automated Placement and Route (APR) using Cadence or Synopsys EDA tools
Static Timing Analysis (STA) using Cadence or Synopsys EDA tools
SoC design with MBIST