3D-IC STCO Physical Design Engineer
The future of Moore's Law: 3D-IC STCO. Link
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in pathfinding as a holistic design co-optimization across the product stack from system architecture to silicon as we extend DTCO to STCO. The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System
Run place and route to design convergence to establish STCO 2D-3D Physical design baseline, assess quality, perform design analysis and 3D PPA design co-optimization
3D EDA evaluation and methodology development.
Inter chiplet analysis and validation with Synopsys 3D-IC Compiler and Cadence 3D Integrity
Identify design optimization opportunities: silicon, package, EDA, architecture configuration, methodology, etc.
Analyze architecture critical paths to identify how to best take advantage of this technology
Identify machine learning opportunities for further optimization
Highly independent and self motivated
Creative, Out of the box thinker
This is an internship and compensation will be given accordingly based on candidate education level and internship duration. Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.Qualifications
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Actively pursuing a MS or PhD degree in Electrical, Computer Engineering or related STEM field.
3+ months of experience with the following:
Physical design, Automated place and route (APR)
Tools, flow and Methodology (TFM) for Design technology co-optimization and PPA
Good understanding of semiconductor physics
Understanding of design methodology and tools features for 2.5D/3D chiplet integration
Experience with high-performance cores