SoC timing & FCT integration BackEnd
We're looking for SoC timing & FCT integration DE to join our team of Full Chip Timing Backend Integration which is a part of the C2DG Design group.
What will you do in this role:
Static timing analysis work with POs & BU data integration to FCT models and debug.
Be responsible for arch timing paths to enable SoC FCT convergence.
You will work closely with worldwide CPU design teams on FC timing flows.
If you want to leave your marking on future FC timing - join us!Qualifications
3-5 years of experience in Hardware Backend design and STA
B.SC in Electrical Engineering or Computers Engineering or Computer and Software EngineeringInside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core ™, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.htmlWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.