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Signal Integrity Engineer

Guadalajara, Mexico Job ID JR0235964 Job Category Engineering Work Mode Hybrid Experience Level Entry Level
Job Description

We are responsible for developing the platform interconnect design guidelines for state-of-the-art server platforms, which support the latest Intel Xeon processors and other server products.

In this position, you will be working with a team of Signal Integrity Engineers and will be developing interconnect interface solutions.

Your scope of responsibilities will include but are not limited to:

  • Engaging with silicon designers platform, designers package, designers electrical, validation teams, and external customer support teams
  • Performing modeling and simulation of highspeed IO (Input-Output) interconnect channels
  • Developing package and platform design guidelines
  • Defining and evaluating circuit design features required to support interconnect performance requirements
  • Creating signal measurement test plans and reviewing measurement results
  • Correlating measurements to simulations
  • Supporting signal integrity tool and methodology development

Behavioral traits:

  • Team player skills and willingness to learn

Qualifications

You must possess the below minimum qualifications to be considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Candidate must possess a Bachelor's, Master's, or Ph.D. degree in Electrical Engineering or a related STEM field (documentation related to Bachelor's degree completion will be required)
  • Advanced English level.

Preferred Qualifications:

  • Signal Integrity experience supporting highspeed differential signals and memory interfaces such as PCIe Ethernet DDR
  • Fundamental knowledge of transmission line theory and highspeed Printed Circuit Boards PCB design
  • Experience with EDA Tools Mentor Graphics Cadence etc
  • Experience with simulation tools MATLAB, HSpice, and ADS
  • Knowledge of Intel Architecture
  • Design of Experiments (DOE) and statistical knowledge and experience would be an added advantage
  • Transmission line modeling using Field Solvers Ansoft 2D HFSS, Q3D, and CST electromagnetic simulator
  • Lab equipment such as TDR VNA digital oscilloscopes and logic analyzers
  • Experience with silicon device modeling methods such as IBISAMI or Verilog A
  • PCB layout process and methodology
  • Experience using scripting languages e.g. Python, PERL, etc
  • Board-level system architecture basic silicon design IO structures and topologies

A candidate who accepts an offer of employment is required to present their own personal identification information and numbers for the following:Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.


Inside this Business Group
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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