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SOC Design Engineer

Folsom, California Job ID JR0232980 Job Category Software Engineering Work Mode Hybrid Experience Level Experienced
Job Description

In the FPGA/Emulation team, your role will be of FPGA/Emulation engineer to develop Field Programmable Gate Array (FPGA) and/or emulation models and solutions for next generation IP technology and SoC designs. You will work closely with architecture, design, IP validation and software teams in order to meet project goals.

In this role, responsibilities include, although not limited to:

  • Develop FPGA/emulation models from Register Transfer Level (RTL) designs using FPGA/Emulation synthesis and place and route tools.
  • Design and develop interfaces between FPGA/emulation model to software or external hardware using RTL.
  • Bring up and debug the FPGA/emulation model in simulation and hardware platforms.
  • Develop tests to validate the functionality of the FPGA/emulation model both in simulation using System Verilog and on hardware platform using Python.
  • Develop automation flows to integrate and build FPGA/Emulation models in Linux environment using Python/Tcl/Perl.
  • Communicate with architecture/design/validation/software teams to debug and isolate issues found on the FPGA/emulation models.


In the IP System Validation role, you will define validation strategies, test plans, and methodologies for pre and post silicon functional end to end validation of IPs.

In this role, responsibilities include, although not limited to:

  • Developing and running tests in emulation and post silicon environments to verify that the system meets specification requirements.
  • Finding and implementing corrective measures for failing tests.
  • Debug failures in complex systems in both pre- and post-silicon environments.
  • Your key role will be to find HW bugs in the IP.
  • You will work closely with FPGA/Emulation, Software and Design teams.
  • You will also work on many new initiatives to improve validation efficiency and validation coverage.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:


The candidate must have a Bachelor's, Master's or PhD degree in Electrical/Computer Engineering or Computer Science and 2+ years of experience in:

  • Modern programming languages (C/C++).
  • Computer System Architecture/Intel architecture and/or micro-architecture with knowledge of processor, chipset, memory, I/O-subsystems, and bus protocols (one of these- USB, PCIe, Display Port, Type C, PCIe, IOSF, AMBA Bus, Low speed IOs, DDR).
  • Experience debugging complex platform like HW, SW/FW and environment issues.
  • VLSI or Auto Place and Route Experience.
  • Static Timing Analysis.
  • Experience resolving IP RTL bugs.


Preferred Qualifications:

  • Silicon/FPGA/emulation modeling and debug experience.
  • Knowledge of ARM, RISC-V is a plus.
  • Familiar with DMA architecture.
  • Familiar with Firmware development.
  • Familiar with working in Linux development environment is a plus.
  • Understanding of a subsystem HW/SW stack, including the silicon, all onboard HW components and connectors, external or plug-in adapters and devices, drivers, and applications
  • Debugging Test Failures/sightings using a variety of Debug Tools to perform characterization of the issue and identify the failing component. This will involve hands on experience in source-level debugging, oscilloscope and/or bus analyzers.

Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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