Skip to main content

SOC Design Engineer: Chipsets SOC Front-End Design

Folsom, California; Santa Clara, California Job ID JR0224656 Job Category Engineering Work Mode Hybrid Experience Level Entry Level
Job Description

Come and be a part of the team creating SoC and chip-set designs and products for Intel Architecture. This position is a role within the Chipsets Silicon Group SOC Front-End Design team, building SoC products for client and server markets. In this position, the Engineer will perform integration and validation of IP designs at the SOC level. The work will include features and behaviors fundamental to the platform, as well as interoperability with the other IPs and blocks in the SOC and platform. The engineer will work with, and gain exposure to, specialist teams and engineers including full-chip, micro-architecture, validation architecture, emulation modeling and validation, IP design, and structural/physical design; will gain exposure on platform architecture, design, and features; and will participate in debug at various level of the hierarchy.

In addition to the qualifications listed below, the ideal candidate will demonstrate the following behavioral traits:

  • Excellent communication skills
  • Willingness to work in a team
  • Leadership skills

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:

The candidate must possess a Master's degree in Electrical or Computer Engineering, or a Bachelor's degree in Electrical or Computer Engineering with 1+ years of experience in the following:

  • Computer Architecture / HW development

  • Simulation-based debug (VCS, Verdi, DVE)

  • System Verilog / OOP; exposure to OVM/UVM

  • Exposure to SOC-level design/integration and/or validation


Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US,Santa Clara


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

  • CMOS Reliability R-D Engineer (SK) Folsom, California Apply Now
  • SOC Design Engineer: Chipsets SOC Front-End Design Multiple Locations Apply Now
  • IP Logic Design Engineer Multiple Locations Apply Now
View All Jobs

No jobs have been viewed recently.

View All Jobs

No jobs have been saved.

View All Jobs