Physical Design Engineer
In this position as a Graphics Hardware Physical Design Engineer, you will be part a world class IP physical design team developing groundbreaking high-performance GPU IPs that are targeted for high-end graphics, gaming, artificial intelligence, media processing and more.
This is a great opportunity to join a talented team that is innovating in ASIC implementation and verification of multimillion gate designs in advanced process nodes across multiple foundries.
Your responsibilities may include, but are not be limited to:
- All aspects of physical design implementation ranging from floor planning, synthesis, APR, clock tree, multi-power and routing leading to final GDS for graphics blocks
- Verification and signoff ranging from static timing analysis, formal verification, reliability, power crossings and layout verification
- Development of the Physical design methodologies, tool implementation and flow automation for APR and signoff
- Optimization for improving the product level parameters such as power, frequency, and area
Minimum Skills and Experience:
A Bachelor's or degree in Electrical/ Electronics/Computer Engineering with 3+ years of educational level research and/or relevant job/internship experiences.
Your Experience Must Be in One, or More, of the following areas:
- Academic coursework in Logic design / VLSI / ASIC Design & Architecture
- ASIC physical design implementation and tape out
- Automation skills through Unix, Linux, Perl and TCL programming
- Proficiency with one or more of the following Industry standard EDA tools: Fusion Complier, Genus, Innovus, Primetime, Tempus, StarRC, Spyglass, RedHawk, LEC Formality, etc
Preferred skills and experience that will make you stand out:
- Master’s degree in Electrical/ Electronics/Computer Engineering
- Knowledge/experience in one or more of ASIC style design flows - floorplanning, synthesis, place & route, layout verification, extraction, static timing analysis, formal verification, Power Grid, EM, IR, Power delivery
- CAD flow development and methodology definition for APR Auto Place and Route and STA Static Timing analysis on leading technologies
- Power performance area (PPA) optimization through logic-design and EDA tool options
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