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Physical Design Engineer - Returnship

Folsom, California; Phoenix, Arizona; Santa Clara, California Job ID JR0231741 Job Category Contract Employee Work Mode Hybrid Experience Level Contract
Job Description

Have you taken a career break and are now interested in returning to the workforce? Intel is offering a 20-week paid returnship for experienced professionals ready to return to the workforce. If you have at least 3 years of professional experience and have taken a career break for 2+ years for any of the following, but not limited to reasons we welcome, you to apply:

  • Starting or raising a family

  • Military service/military spouse

  • Community service/volunteer work

  • Caring for a family member or self

  • Teaching

  • Other

At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. Through this program you will have the opportunity to revamp your skills, update your resume with new skills and experiences as well as make connections with others transitioning back into the workforce.

This position is hybrid in Folsom, CA or other Virtual US locations during the 20-week returnship program.


As a Physical Design Engineer, you would be responsible for creating custom layout for bottom-up elements of chip design including, but not limited to:

  • Transistor, Cell, and Block-level custom layouts, floor plans, abstract view and schematic-to-layout generation.

  • Layout verification and debug to enable physical design development, including observing and intercepting parasitic extraction results.

  • Producing wire load models, Quality clock generation, custom polygon editing, floor-planning, full-chip assembly, packaging and verification.

  • Troubleshooting a wide variety of issues including difficult design concerns and apply proactive intervention.

  • Scheduling, staffing, executing, and verifying complex chips development and execution of project methodologies and/or flow developments.

  • Requires knowledge and practical application of analog/custom physical design tools and methodologies.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

This position is not eligible for Intel immigration sponsorship.


Minimum Qualifications

  • Candidate must have a Bachelor's degree in Electrical Engineering (EE) or Computer Engineering (CE) or Computer Science (CS) with 3 years industry experience or Master's degree in Electrical Engineering (EE) or Computer Engineering (CE) or Computer Science (CS) with 2 years of industry experience.

  • Electronic circuit functionality and behaviors.

  • Complementary metal oxide semiconductor (CMOS)and Very Large Scale Integration (VLSI )component design principles.

  • Candidates must have taken a career break for 2 or more years.


Preferred Qualifications:

  • Experience with Electro-migration, self-heating, and other reliability concepts and knowledge of Custom Physical Design requirements for digital, mixed-signal and analog circuitry.

  • Experience in various verification flows for DRC and LVS tools.

  • Experience in extraction tools and how to use that feedback to guide physical design.

  • Experience in Analog Physical Design requirements for digital, mixed-signal, and analog circuitry.

  • Experience in Cadence design flow, Virtuoso, and/or comparable tools.


Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US,AZ,Phoenix;US,CA,Santa Clara


Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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