Physical Design Engineer - Returnship
Have you taken a career break and are now interested in returning to the workforce? Intel is offering a 20-week paid returnship for experienced professionals ready to return to the workforce. If you have at least 3 years of professional experience and have taken a career break for 2+ years for any of the following, but not limited to reasons we welcome, you to apply:
Starting or raising a family
Military service/military spouse
Community service/volunteer work
Caring for a family member or self
At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. Through this program you will have the opportunity to revamp your skills, update your resume with new skills and experiences as well as make connections with others transitioning back into the workforce.
This position is hybrid in Folsom, CA or other Virtual US locations during the 20-week returnship program.
As a Physical Design Engineer, you would be responsible for creating custom layout for bottom-up elements of chip design including, but not limited to:
Transistor, Cell, and Block-level custom layouts, floor plans, abstract view and schematic-to-layout generation.
Layout verification and debug to enable physical design development, including observing and intercepting parasitic extraction results.
Producing wire load models, Quality clock generation, custom polygon editing, floor-planning, full-chip assembly, packaging and verification.
Troubleshooting a wide variety of issues including difficult design concerns and apply proactive intervention.
Scheduling, staffing, executing, and verifying complex chips development and execution of project methodologies and/or flow developments.
Requires knowledge and practical application of analog/custom physical design tools and methodologies.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
This position is not eligible for Intel immigration sponsorship.
Candidate must have a Bachelor's degree in Electrical Engineering (EE) or Computer Engineering (CE) or Computer Science (CS) with 3 years industry experience or Master's degree in Electrical Engineering (EE) or Computer Engineering (CE) or Computer Science (CS) with 2 years of industry experience.
Electronic circuit functionality and behaviors.
Complementary metal oxide semiconductor (CMOS)and Very Large Scale Integration (VLSI )component design principles.
Candidates must have taken a career break for 2 or more years.
Experience with Electro-migration, self-heating, and other reliability concepts and knowledge of Custom Physical Design requirements for digital, mixed-signal and analog circuitry.
Experience in various verification flows for DRC and LVS tools.
Experience in extraction tools and how to use that feedback to guide physical design.
Experience in Analog Physical Design requirements for digital, mixed-signal, and analog circuitry.
Experience in Cadence design flow, Virtuoso, and/or comparable tools.
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