IP Logic Design Engineer - Graduate Intern
The Foundational Security Hardware team is looking for future technical leaders and experts. Position requires knowledge in digital logic design, computer architecture, and/or exposure to pre/post-silicon validation. Candidate will be responsible for logic design of different blocks in the Security IP team.
In this role responsibilities include, although not limited to:
Defining and implementing the design in System Verilog.
Applying various strategies/tools/methods.
Checking the design for synthesizability, DFX, clock crossing, power, performance implications.
The candidate must work closely with Architects, Micro-architects and Validation teams in determining the proper implementation strategy for new design, defining and feedback on specifications, develop Open Box Coverage plans, review design collateral for efficiency/coverage.
In addition to the qualifications listed below, the ideal candidate will demonstrate the following traits:
Excellent communication and organization skills are critical.
Technical leadership skills.
Passion for design tools and methodologies.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
The candidate must be pursuing a Master's or Ph.D. in Electrical Engineering or Computer Engineering.
6+ months of experience in:
Digital logic design tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power.
Knowledge of critical PC IO subsystems (e.g. PCIe, USB, SATA, UART, SPI ...).
Knowledge of HW/SW Security mechanisms and cryptography.
Knowledge of IO Controllers and Design and worked with standard buses / bridges such as AHB / OCP / AXI.
Knowledge of Low power / High Performance Designs and Practices.
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