CIT Logic Design Engineer - Returnship
Have you taken a career break and are now interested in returning to the workforce? Intel is offering a 20-week paid returnship for experienced professionals ready to return to the workforce. If you have 5+ years of professional experience and have taken a career break for 2+ years for any of the following, but not limited to reasons we welcome you to apply:
Starting or raising a family.
Military service/military spouse.
Community service/volunteer work.
Caring for a family member or self.
At Intel we are excited to have a Return-to-Work program because we appreciate the skills individuals who are returning to work can offer. Through this program you will have the opportunity to revamp your skills, update your resume with new skills and experiences as well as make connections with others transitioning back into the workforce.
This is an exciting time to be at Intel - come join our Chipsets Ingredients Team which is part of the Chipsets Silicon Group (CSG). Intel is transforming and so is CSG. Here at CSG we create products that empower people to live a better life.
We at CIT are looking for a highly motivated logic/RTL design engineer who will be responsible for the definition and implementation of clocking solution for client and server chipsets in cutting edge internal and external technology nodes. In this unique role the scope of learning opportunities, contributions and influence expands over on-die, multi-die and system level clocking solutions. As system level clocking protocols are the backbone of modern multi-die power management schemes, the role naturally expands into great exposure and contribution opportunities into low-power architecture and design. You will be responsible for the development of all new clocking IPs for the various market segments that CSG caters across Intel.
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Your responsibilities will include, but not be limited to one or more of the following aspects of the design flow which encompasses all aspects of logic design methodology:
Feature feasibility study, performance analysis and micro architecture of latest feature requirement.
Digital design of a wide variety of logic functions, with emphasis on multi-clock and multi-power domain designs.
Register Transfer Level (RTL) HDL design feasibility, development and debug.
Co-development of design test plan and validation strategy with validation team.
Providing IP integration support to SoC customers.
In addition to the qualifications listed below, the ideal candidate will demonstrate the following traits:
Technical leadership with communication, interpersonal and problem-solving skills.
Motivated, self-directed, and willing to work effectively both independently and as a team.
This position is hybrid at the Folsom CA, Santa Clara CA, Arizona or Virtual during the 20-week returnship program.
This position is not eligible for Intel immigration sponsorship.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
The candidate must possess a degree in Electrical, Computer, or any engineering related field and experience in:
Microprocessors, computer system architecture VLSI design
Digital state machine architecture and logic design
Simulation-based debug (VCS, Verdi, DVE)
Exposure to Static Timing Analysis, timing convergence and synthesis
Candidates must have taken a career break for 2 or more years.
RTL quality checks (Lintra, CDC, VCLP)