Sr. Pre-Silicon Validation Engineer
The Graphics and Throughput Computing Hardware Engineering (GTCHE) Division, within the IAGS (Intel Architecture, Graphics and Software) Supergroup, is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs (GPUs), targeting both Client Device and Datacenter markets. The GTCHE organization is at the center of Intel’s push into the discrete Graphics SoCs market segment targeting next-generation applications such as High-performance Exascale computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming, etc.
In this position you will be part of a world-class Silicon design organization working with a team of highly talented engineers working on cutting-edge IP/SoC architectures, advanced Silicon design and process technologies, with tremendously exciting opportunities for industry-leading engineering innovations.
- Leading major cluster/top level verification, developing test environment, verification specification documentation and working with cross-functional engineering teams on architecture, design and verification.
- Ownership/coding/enhancement of functional scoreboards/agents/sequences/monitors
- Responsible for understanding architecture spec and deriving test cases / testplans
- Help/drive throughput test case setup/analysis/report of the DUT
- Define functional coverage/code/hit it through sequence enhancement and newer/directed test cases.
- Working closely with architecture and RTL designers on verifying the functionality correctness of the design; Participating in the development of Architecture and Microarchitecture specifications for the Logic components; Working closely with Validation Architect in defining validation strategy and reviewing test plan.
- Developing test plans and test environments; Developing tests in assembly, C, or SV according to test plans; Developing coverage monitors and analyze coverage to ensure all the test cases in the plans are covered.
- Develop new test bench methodologies and components to improve simulation efficiency
- Guide and mentor junior engineers
Bachelors or Masters degree in Electrical, Electronics or Computer Engineering with 10-15 years of relevant industry experience including at least 5 years of pre-Si Validation experience
Relevant ASIC design/validation experience in front end processes including RTL functional, performance and power verification
Good knowledge of digital logic design, chip architecture and microarchitecture.
- Strong leadership skills and has the ability to work independently
- Expertise in verification of design blocks (IP) for system-on-chip (SoC) components
- Expertise in System Verilog and OVM or UVM based verification methodologies
- Experience in OOP concepts, coverage based random validation
- Experience in one/more of the following areas PCIe, USB
- Knowledge of scripting, SVA, UPF validation
- Knowledge of IO interconnect, memory controllers, CPU architecture is a plus
- Knowledge of considerations for performance, power and cost optimization is desirable
- Experience with advanced verification techniques such as formal and assertions a plus.
- Needs to be a key team player, while being highly energetic and motivated, independent and self-driven