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Senior Physical Design Engineer ( Synthesis , Placement and Routing)

Bengaluru, India Job ID JR0231516 Job Category Engineering Work Mode Hybrid Experience Level Experienced
Job Description
Design Enablement team at India, is part of Technology Development group, having charter to develop methodology for advance process nodes, providing opportunity, to be among the first one to work on latest technology. This role, in Design Enablement, is for experienced Individual contributor for Physical design of digital blocks using Synthesis -Automatic Placement and Route flow, from RTL to GDS , including sign off for Timing, Reliability and Layout verification.
Candidate is expected to develop and support solutions in a wide variety of activities related to Synthesis, Floor planning, Placement, Clock Tree Synthesis, Routing, Timing convergence, Scan, Hard Macro integration and Physical convergence. Candidate will be responsible for, constraint development, flow optimization to meet design requirements, by working with RTL developers, CAD team and EDA vendors.

This role also requires having understanding of analysis and sign off flow for project, and candidate should be able to provide solution to team, by working with CAD team and EDA vendors. This role requires transparent and clear communication and mindset to excel at work in collaborative environment with teams in other domains and Geographic locations.
Qualifications
Candidate must have 5+ years of relevant experience with Master's degree (M.Tech/MS) in Microelectronics/ Electronics Engineering or equivalent qualification from reputed institute.

Candidate should have worked on block closure using industry standard tool for SAPR flow. He should have good knowledge of Floor planning, Power planning, Placement, Clock Tree Synthesis and Routing. He/ she should be well versed with multiple optimization options for design closure and expected to provide solution to team for complex implementation issues. Candidate should have good understanding of timing concepts and expected to analyze the constraint used for design and its impact on timing closure. He/ She should have worked on Layout closure for the blocks, ensuring DRC, LVS, density and Antenna requirements are met as per specification. He/ She should have good knowledge of top-level Integration issues to ensure block level deliverables meet project level requirements for timing and layout closures.

He/ She should have good knowledge of VLSI, Digital electronics and understanding of semiconductor devices, circuits, timing closure of digital design. Understanding of fabrication and process technology will be added advantage. Any scripting language experience, like perl, TCL, python would be plus point.

He / She should have good analytical, problem-solving skill for debugging issues faced at work. He / She should have proactive and transparent communication. He / She should be having mindset to work in diverse and collaborative environment with teams in different domains and Geos

Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Maggie, Offensive Security Researcher

Maggie Offensive Security Researcher

“I’ve always wanted to do something that changes the world — at Intel, I feel appreciated, and I’ve gained more confidence in myself. It makes me feel like I’m capable of doing great things.”

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