Physical Design Lead
We are an end-to-end design team, based in Bangalore part of Intel Labs. We are looking for highly motivated individuals with a passion to work closely with design teams and creatively impact design flows and development.
You will be responsible for the complete physical/back-end design convergence of complex SOC partitions starting from Synthesis till Tape-out. Along with the partition ownership you would be responsible for enhancing/customizing
the PD flow and methodology based on the project needs.
Your responsibilities will include the following:
- Working closely with the Design and Micro-Arch team in studying and analyzing the micro-arch specifications
- Develop timing constraints and provide feedback based on RTL synthesis
- Own IP block level floor planning, CTS and P and R optimizations to meet design specs. Verifying and ensuring that Area/Power/Performance specifications are met
- Verify design for all physical design verification flows which include STA, FEV, IR drop, Noise, Low power checks and DRC and LVS
- Understand Intel physical design flows and debug/enhance the methodology as per project needs
- If required apply research-based learnings to improve design convergence
You should possess a Master's degree in EE with 7+ years of experience or a Bachelor's degree in EE with 9+ years of experience in VLSI physical design.
Additional qualifications include:
- Knowledge of microelectronic designs, semiconductor device physics, CMOS process and physical layout. Good understanding of complete Physical design flow.
- Hands-on experience in converging complex blocks from RTL to GDSII (greater than 500K instances) with embedded macros and low power implementation. Experience with PCIE or LPDDR phy integration is an add-on.
- Tape out experience with good understanding of latest process nodes DRC's (10nm, 7m/5nm).
- Experience in automation for design methodology and flow development. Leverage debugging skills and come up with technical solutions independently.
- Experience in logic synthesis, timing constraint development, floorplan, power plan, CTS, routing and timing closure and DRC and LVS closure.
- Experience in backend verification flows like STA, FEV, IR-drop analysis and low power verification.
- Good hands-on knowledge on EDA tools like Synopsys FC/DC-ICC2, Primetime, Spyglass, Cadence LEC, Ansys Redhawk and CalibreDrv/ICWEBV2.
- Good knowledge in scripting languages like Tcl and Shell (csh/tcsh/bash). Hands-on Experience in developing utilities in TCL/TK. Familiarity with hardware description language such as Verilog or System Verilog.
- Good team player who communicates clearly and can work efficiently with cross functional/geo teams