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DFD Architect

Bengaluru, India Job ID JR0235483 Job Category Engineering Support Work Mode Hybrid Experience Level Experienced
Job Description
Architect the debug capability and infrastructure for FPGA projects. Come up with High level Architecture and Micro-Architecture Spec for Design for Debug (DFD) for FPGA products. Evaluates the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly. Define, document and test processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or software compatibility. Work closely with DFD micro-Architect, design, test and pre/post silicon validation teams to define debug requirements and strategies. Responsibilities will include, but not limited to Architecting the DFD features, micro-architecting and design of the DFD features. Train and mentor junior engineers and the team for upskilling in the area of DFD. Play a vital role in post-silicon debugs with validation team and monitor the DFD execution throughout the silicon lifecycle from Arch to implementation to pre-sil Val to timing closure to Tape-out and post-si debug support.
Qualifications
The candidate must possess a minimum of Bachelor's Degree in Electronics/Computer Engineering or equivalent. Industry experience of minimum 14 years in relevant field. The candidate must have a successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in an ambiguous and dynamic business environment. Must have � Strong interest in Design for Debug Architecture and domain design. � Experience in Architecture, micro-architecture and RTL Design is essential � Familiarity with Design for Debug functionality or post silicon debug work is a plus. Nice to have � Experience in architecture , micro architecture and design of DFD features at IP or SoC level.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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Maggie Offensive Security Researcher

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