Sr. E-Core CPU Physical Design & Verification CAD Engineer – RTL2GDS Standard Cell Level Flows
Do you want to engineer the future? The E-core team is powered by some of the brightest and most innovative minds in the industry and we need more!
Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person.
We are designing future generations of high-performance Intel E-core CPUs using the most advanced and innovative process technologies.
These industry leading performance per watt CPUs help power the latest generation of Intel laptops and desktops, 5G base stations, micro-servers, Chromebooks for students and other Artificial Intelligence and Machine Learning devices.
If you are looking to grow and develop your skillsets while be surrounded by highly motivated and knowledge teammates then this is the organization for you!
Atom/E-Core CPUs are:
Powering the latest Intel i9/i7/i5/i3 SOC 12th Generation laptops, desktops and high-end gaming platforms
The engine that is driving 5G communications by serving as the base-station that delivers essential data from your electronic devices across the world at maximum bandwidth
The brains in Artificial Intelligence (AI) and machine learning in the Amazon Echo Show and other devices
The CPUs inside the latest Google Chromebooks that is enabling a full virtual learning experience for many students during the COVID crisis
Role responsibilities include:
Your responsibilities in this highly visible role will include, but not be limited to:
Defining, implementing and drive project execution by supporting the methodologies and EDA tools necessary to verify backend signoff flows using standard-cell based designs
Work closely with Physical Designers to drive solutions in 1 or more of areas, including Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Active/Dynamic/Leakage Power Analysis, LVS, Power-Rail Integrity, Extraction or ECO
Develops and tests Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies including driving new innovations to EDA tool vendors
Develop custom optimized solutions to address design requirements for leading-edge process technologies
Validate and drive continuous innovation of PDK technology, library files and other collaterals used for standard cell design, layout, and signoff with EDA CAD tools
Proficiency in benchmarking QOR and provide design guidance for better power optimization and/or techniques for frequency improvement and/or tool runtime improvement
Create flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies
Contribute to the development of multidimensional designs involving the layout of complex integrated circuits
Document and help with guidelines/specs
The ideal candidate should exhibit the following behavioral traits:
Good inter-personal, clear communication and good teamwork skills
A can-do attitude driven by research and thriving on challenges
Self-motivator with strong problem solving skills
Willing to handle multiple projects simultaneously and prioritize to project timelines
Good communicator who can accurately perform a deep-dive to assess, and summarize issues to management
Takes ownership to provide recommendations and drives solutions through to completion
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have a Bachelor's degree in Electrical/Computer Engineering with 4+ years of experience - OR - a Master's degree in Electrical/Computer Engineering with 3+ years of experience - OR - a PhD in Electrical/Computer Engineering with 2+ years of experience in:
Physical Design and Verification Tools, Flows and Methods used in VLSI back-end standard cell and/or custom-transistor based designs
Using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Synopsys, Cadence and/or Mentor Graphics in one of more of the following areas of: STA, Power, ECO, Noise and/or ERC flows
Signoff aspects in STA for timing closure (OCV, constraints, parasitics, hyperscale, UPF), LVS, Static Power Analysis or Signal integrity analysis (Noise, SI-crosstalk)
Desire to deep-dive into timing paths, perform QOR difference analysis and identify key issues
Linux environments and basic shell scripting
Expertise is a must in one or more scripting languages such as Python, Perl and/or Tcl
Standard-cell liberty format syntax
Standard formats from 1 or more of gate-level netlist, standard parasitic formats and/or SDC constraints
EDA tool Tcl API coding
Advanced programming data structures
2+ years of experience in one or more of the following:
- IP providers and consuming content
- Digital circuit device-level SPICE modelling; SPICE simulations and transistor-level signoff verification concepts
- Leading/Mentoring junior team members or prior interns
- Machine-learning methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement
- Timing and power ECO techniques and implementation